Southbridge diagram


The Southbridge, also known as an I/O Controller Hub (ICH) or a Platform Controller Hub (PCH) in Intel systems (AMD, VIA, SiS and others usually use 'southbridge'), is a chip that implements the "slower" capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. The southbridge can usually be distinguished from the northbridge by not being directly connected to the CPU. Rather, the northbridge ties the southbridge to the CPU.


Because the southbridge is further removed from the CPU, it is given responsibility for the slower devices on a typical microcomputer. A particular southbridge will usually work with several different northbridges, but these two chips must be designed to work together; there is no industry-wide standard for interoperability between different core logic chipset designs. Traditionally this interface between northbridge and southbridge was simply the PCI bus, but since this created a performance bottleneck, most current chipsets use a different (often proprietary) interface with higher performance.


The name is derived from drawing the architecture in the fashion of a map and was first described as such with the introduction of the PCI Local Bus Architecture into the PC platform in 1991. The authors of the PCI spec at Intel viewed the PCI local bus as being at the very center of the PC platform architecture (i.e., at the Equator). The so called Northbridge extends to the north of PCI in support of CPU, Memory/Cache and other performance critical capabilities. Likewise the Southbridge extends to the south of the PCI bus backbone and bridged to less performance critical I/O capabilities such as the disk interface, audio, etc. The PCI unit would be at the top of the map at due north. The CPU would be connected to the chipset via a fast bridge (the northbridge) located north of other system devices as drawn. The northbridge would then be connected to the rest of the chipset via a slow bridge (the southbridge) located south of other system devices as drawn. Note that current day PC platform architecture has replaced PCI with a faster I/O backbone however the bridge naming convention remains.


The functionality found on a contemporary southbridge includes:

  • PCI bus. The PCI bus support includes the traditional PCI specification, but may also include support for PCI-X and PCI Express.
  • ISA bus or LPC Bridge. Though the ISA support is rarely utilized, it has interestingly managed to remain an integrated part of the modern southbridge. The LPC Bridge provides a data and control path to the Super I/O (the normal attachment for the keyboard, mouse, parallel port, serial port, IR port, and floppy controller) and FWH (firmware hub which provides access to BIOS flash storage).
  • SPI bus. The SPI bus is a simple serial bus mostly used for firmware (e.g., BIOS) flash storage access.
  • SMBus. The SMBus is used to communicate with other devices on the motherboard (e.g. system temperature sensors, fan controllers).
  • DMA controller. The DMA controller allows ISA or LPC devices direct access to main memory without needing help from the CPU.
  • Interrupt controller. The interrupt controller provides a mechanism for attached devices to get attention from the CPU.
  • IDE (SATA or PATA) controller. The IDE interface allows direct attachment of system hard drives.
  • Real Time Clock. The real time clock provides a persistent time account.
  • Power management (APM and ACPI). The APM or ACPI functions provide methods and signaling to allow the computer to sleep or shut down to save power.
  • Nonvolatile BIOS memory. The system CMOS, assisted by battery supplemental power, creates a limited non-volatile storage area for system configuration data.
  • AC97 or Intel High Definition Audio sound interface
  • Baseboard Management Controller

Optionally, the southbridge will also include support for Ethernet, RAID, USB, audio codec, and FireWire. Rarely, the southbridge may also include support for the keyboard, mouse, and serial ports, but normally these devices are attached through another device referred to as the Super I/O.

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